High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking chips vertically and interconnecting the chips using through substrate vias (TSVs) between an interface (I/F) chip and core chips. FIG. 1 is a block diagram of an apparatus including a memory controller 1 and a memory device 10. The memory device 10 may include an interface chip 2 and a plurality of core chips 3 CC0-CC3. Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and a wide-I/O dynamic random access memory (DRAM).
In a 3D memory device as described, each chip, such as the interface chip or each core chip, may include a first-in-first-out (FIFO) type of buffer for write data. The FIFO type of buffer may receive write data responsive to a write data strobe signal (WDQS) and may provide an output signal responsive to an output clock signal. Thus, in the 3D memory device, the write data may be transmitted via two FIFO type of buffers, one in the interface chip and the other in the corresponding core chip. However, the FIFO type of buffers delays the output signal because of waiting for a timing of being output responsive to the output clock signal. Furthermore, the FIFO type of buffer in the interface chip may be redundant for being responsive to an output clock signal in the interface chip, because another FIFO type of buffer in the core chip that receives the write data from the interface chip provides the write data responsive to an output clock signal in the core chip. Thus, the write data from the FIFO type of buffer in the core chip is eventually adjusted based on the output clock signal in the core chip.
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance DRAM interface and vertically stacked DRAM. A typical HBM stack of four DRAM core chips contains two channels per chip, and each of the two channels includes 128 bit I/Os. The typical HBM stack may contain a total of eight input/output channels and a width of 1024 bits in total. An interface (I/F) chip of the HBM provides an interface with the eight input/output channels, which function independently of each other. Thus, the above 3D memory device may be include a substantially large number of data terminals (DQs) (e.g., 1024 DQs) in the interface chip. Because the FIFO type of buffer is provided for each data terminal, the large number of the FIFO type buffers may cause a larger layout size, in addition to the delay to write data signals provided to the core chips.